# === 项目配置 ===
PYTHON :=python3
COVERAGE_ROOT = coverage
GCC_COVERAGE = 1
VERILATOR_COVERAGE = 1

TOPLEVEL_LANG = verilog
SIM_BUILD = build
VERILOG_SOURCES = rtl/counter.sv
TOPLEVEL = counter
MODULE = tests.tb_top
SIM = verilator
VERILATOR_ARGS = -Isrc --trace --coverage --coverage-line --coverage-toggle --coverage-user
EXTRA_ARGS = $(VERILATOR_ARGS)
CFLAGS += -ftest-coverage -fprofile-arcs
LDFLAGS += -lgcov
COVERAGE_DIR = $(SIM_BUILD)/coverage_data

# === 关键修复 ===
# 使用标准的 Cocotb 配置机制

# 包含标准 Makefile.sim
include $(shell cocotb-config --makefiles)/Makefile.sim

# === 自定义任务 ===
coverage:
	@echo "生成详细的覆盖率报告..."
	verilator_coverage --annotate coverage-annotated $(COVERAGE_ROOT)/coverage.dat
	verilator_coverage --html coverage-report $(COVERAGE_ROOT)/coverage.dat
	@echo "Verilator HTML 报告: coverage-report/index.html"
	lcov --capture --directory $(SIM_BUILD) --output-file $(SIM_BUILD)/coverage.info
	genhtml $(SIM_BUILD)/coverage.info --output-directory gcc-coverage
	@echo "GCC 覆盖率报告: gcc-coverage/index.html"
	@echo "文本注释报告: coverage-annotated/"

clean::
	rm -rf $(SIM_BUILD) $(COVERAGE_DIR) $(COVERAGE_ROOT) coverage-report coverage-annotated gcc-coverage
	rm -f results.xml waveform.vcd

wave:
	gtkwave waveform.vcd

test-and-coverage:
	$(MAKE) clean
	$(MAKE) COVERAGE=1
	$(MAKE) coverage